NDLI: Flicker noise behavior of MOSFETs fabricated in 0.5 /spl mu/m fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

Content Provider	IEEE Xplore Digital Library
Author	Ericson, M.N. Britton Jr., C.L. Rochelle, J.M. Blalock, B.J. Binkley, D.M. Wintenberg, A.L. Williamson, B.D.
Copyright Year	1963
Abstract	This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in the Peregrine 0.5 /spl mu/m fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 /spl mu/m to 4 /spl mu/m. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	963
Ending Page	968
Page Count	6
File Size	732769
File Format	PDF
ISSN	00189499
Volume Number	50
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	1f noise Noise measurement CMOS process CMOS technology Detectors Silicon on insulator technology Fabrication Integrated circuit noise Integrated circuit technology Laboratories
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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Noise behavior of MOSFETs fabricated in 0.5 /spl mu/m fully-depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate,, and strong inversion

High temperature DC characterization of fully-depleted 0.5 /spl mu/m SOS-CMOS MOSFETs for analog circuit design

2nd- and 4th-order /spl Sigma//spl Delta/ modulators fabricated in 3.3 V 0.5 /spl mu/m SOS-CMOS for high-temperature applications

A comparative approach of low frequency noise in 0.25 and 0.12 /spl mu/m Partially and Fully Depleted SOI N-MOSFETs

Micropower, 0.35-/spl mu/m partially depleted SOI CMOS preamplifiers having low white and flicker noise

Extremely scaled fully depleted SOI CMOS

Flicker noise in thin film fully depleted SOI MOSFETs

Impact of improved mobility and low flicker noise MOS transistors using accumulation mode fully depleted silicon-on-insulator devices

Noise performance of 0.35-/spl mu/m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-mrad (Si) proton irradiation

Flicker noise behavior of MOSFETs fabricated in 0.5 /spl mu/m fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

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