NDLI: Modeling and analysis of fault tolerant multistage interconnection networks

Content Provider	IEEE Xplore Digital Library
Author	Minsu Choi Park, N. Lombardi, F.
Copyright Year	1963
Abstract	Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation such as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable.
Sponsorship	IEEE Instrumentation and Measurement Society Bureau international des poids et mesures IEEE International Bureau of Weights and Measures (BIPM) URSI NBS Agency Ind. Sci. & Technol., Min. Int. Trade & Ind. Sci. Council Japan International Union of Pure and Applied Physics (IUPAP) NIST NRCC National Conference of Standards Laboratories (NCSL) Allen Osborne Associates Andeen-Hagerling, Inc. Ballantine Lab. Inc. Clarke-Hess Communications Research Corp. Fluke Corporation Guildline Instruments Hewlett-Packard Co. Julie Res. Lab. Inc. Keithley Instruments, Inc. Measurements International Ltd. Canada QuadTech Inc. Quantum Design Inc. Rotek Instrum. Corp. Tegam Inc. Tektronix Inc
Starting Page	1509
Ending Page	1519
Page Count	11
File Size	629110
File Format	PDF
ISSN	00189456
Volume Number	52
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Multiprocessor interconnection networks Switches Testing Degradation Instrumentation and measurement Fault detection Instruments Fault diagnosis Throughput
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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