NDLI: Low pinch-off voltage amorphous silicon junction field-effect transistor: experiment and simulation

Content Provider	IEEE Xplore Digital Library
Author	Caputo, D. de Cesare, G. Lemmi, F. Palma, F. Tucci, M.
Copyright Year	1963
Abstract	In this work, a junction field effect transistor (JFET) based on a-Si:H is presented. The drain-source contacts are made on top of the n-layer of a glass/metal/p/sup +/-i-n structure. The channel conductivity can be modulated by a reverse bias applied to the p/sup +/-i-n junction, which varies the depth or the length of the depletion region. In amorphous silicon, the depletion of doped layers is limited by the high defect density induced by the doping process. Here, the electron concentration of the n-doped layer (the device channel) in a p-i-n amorphous silicon junction is studied by using a one-dimensional finite-difference simulator. The n-channel conductivity is then obtained by integrating the free electron concentration along the drain-source direction. Pinch-off regime is achieved when the n-layer is fully depleted. A JFET with W/L = 400 /spl mu/m/40 /spl mu/m was fabricated. Transistors with pinch-off voltages around -3.6 V and transconductance values of the order of 10/sup -7/ A/V were obtained. Comparison between experimental and modeled output characteristics suggests the presence of a defect-rich layer at the channel-air interface. This is related to the damage induced by the process steps during the device fabrication. The achieved experimental results make the device suitable for applications in linear circuits. In particular, unlike thin film transistors (TFTs), JFETs do not require high-temperature, high-quality dielectric layers, and appear particularly attractive for process on plastic substrates.
Sponsorship	IEEE Electron Devices Society
Starting Page	1559
Ending Page	1561
Page Count	3
File Size	277901
File Format	PDF
ISSN	00189383
Volume Number	50
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	JFETs Conductivity Finite difference methods Semiconductor device modeling Charge carrier density
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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