NDLI: Predicting defect-tolerant yield in the embedded core context

Content Provider	IEEE Xplore Digital Library
Author	Meyer, F.J. Park, N.
Copyright Year	1968
Abstract	We address the problem of predicting the yield of a chip composed of cores. A center-satellite model is used to directly represent observed spatial autocorrelation of integrated circuit spot defects. This model is compared to another (large-area clustering) model that only indirectly represents intrawafer correlation. We illustrate that, when different portions of a chip have different susceptibility to defects, the chip layout will affect the predicted yield. This is particularly relevant when portions of a chip are defect-tolerant because their susceptibility to defects is dramatically different. We illustrate how the yield models can be used to predict the utility of making much of a chip (or an embedded core) defect-tolerant. Two yield points parameterized the models. The one extra parameter of, and the suitability of, the center-satellite model allowed it to track the yield data points with less than 1 /10,000 of the error of the large-area clustering model. However, the simpler large-area clustering model is accurate in some circumstances, especially when the chip area is small.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	1470
Ending Page	1479
Page Count	10
File Size	823663
File Format	PDF
ISSN	00189340
Volume Number	52
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault diagnosis Computer fault tolerance Yield estimation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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