NDLI: A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Content Provider	IEEE Xplore Digital Library
Author	Kopcsay, G.V. Krauter, B. Widiger, D. Deutsch, A. Rubin, B.J. Smith, H.H.
Copyright Year	1993
Abstract	Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	695
Ending Page	711
Page Count	17
File Size	741556
File Format	PDF
ISSN	10638210
Volume Number	10
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inductance Very large scale integration Integrated circuit interconnections Frequency synthesizers Circuit synthesis Wires Sparse matrices Transmission line matrix methods Timing Crosstalk
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Analysis of pulse propagation on high-speed VLSI chips

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

A provably passive and cost-efficient model for inductive interconnects

A comparison of strong and weak distributed transverse coupling between VLSI interconnects

DSM interconnects: importance of inductance effects and corresponding range of length

2.5-dimensional VLSI system integration

Minimization of delay and crosstalk in high-speed VLSI interconnects

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method

Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Similar Documents

Analysis of pulse propagation on high-speed VLSI chips

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

A provably passive and cost-efficient model for inductive interconnects

A comparison of strong and weak distributed transverse coupling between VLSI interconnects

DSM interconnects: importance of inductance effects and corresponding range of length

2.5-dimensional VLSI system integration

Minimization of delay and crosstalk in high-speed VLSI interconnects

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method

Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis