NDLI: DLT replacement and synchronization in the digital hybrid PLL frequency synthesizer

Content Provider	IEEE Xplore Digital Library
Author	Heung-Gyoon Ryu Eung-jin Ahn
Copyright Year	1975
Abstract	The conventional PLL (phase locked loop) frequency synthesizer has a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are a serious problem because the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit which makes the negligible overshoot and much shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. Also, the hardware complexity and power consumption are decreased to about 28%, as compared with the conventional DH-PLL. The high speed switching characteristic in the frequency synthesis process is verified by computer simulation.
Sponsorship	IEEE Consumer Electronics Society
Starting Page	151
Ending Page	156
Page Count	6
File Size	326389
File Format	PDF
ISSN	00983063
Volume Number	48
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Frequency synthesizers DH-HEMTs Frequency synchronization Hardware Energy consumption Voltage-controlled oscillators Circuit synthesis Table lookup Read only memory
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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