NDLI: A unified systolic array design for kernel functions of video compression

Content Provider	IEEE Xplore Digital Library
Author	Poi Lin Tai Chii Tung Liu Jia Shung Wang
Copyright Year	1992
Abstract	In video compression, some kernel functions such as block matching, discrete wavelet transform, vector quantization, etc., are of prime essential, but with a large amount of computation. Recently, many systolic array architectures have been designated for performing each of those functions in real time. In fact, many kernel functions contain the similar computational procedure. If we dissect these functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this brief, by carefully extracting the common computation component, a unified one-dimensional systolic array design that can perform at least the above three functions is presented. In this design, the input data is serial-in to save the amount of pins required, and the data flow are carefully arranged to simplify the interconnection between computation components. When 64 registers are in the on-chip memory, our design can perform three typical functions: (1) the full-search block matching with block size 16/spl times/16 and the search range (-8,7); (2) the 2-D Harr transform with block size 8/spl times/8; and (3) the vector quantization with input vector size 4/spl times/4 and codebook size 256. Since the unified architecture reduces hardware costs, and has a regular hardware structure, it is suited for VLSI implementation for video/image compression applications that require all the functions.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	523
Ending Page	531
Page Count	9
File Size	377233
File Format	PDF
ISSN	10577130
Volume Number	48
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Systolic arrays Kernel Video compression Discrete wavelet transforms Vector quantization Hardware Computer architecture Data mining Pins Data flow computing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in