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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yeong-Dae Kim Jae-Gon Kim Bum Choi Hyung-Un Kim |
| Copyright Year | 1989 |
| Abstract | Focuses on production scheduling in a semiconductor wafer fab producing multiple product types that have different due dates and different process flows. In the wafer fab, wafer lots are processed on serial and batch processing workstations, each of which consists of parallel identical machines. Machines in serial processing workstations process wafer lots one by one, while those in batch processing workstations process several wafer lots of the same recipe at the same time. What needs to be done for production scheduling are lot release control, lot scheduling, and batch scheduling. For these three decision problems, we develop several rules which use information such as order sizes (numbers of lots in orders) and processing status of the wafer lots. To evaluate these new rules, we use a simulation model in which the three decision problems are considered simultaneously. Simulation results show that the new rules work better than existing rules in terms of total tardiness of the orders. |
| Starting Page | 589 |
| Ending Page | 598 |
| Page Count | 10 |
| File Size | 167648 |
| File Format | |
| ISSN | 1042296X |
| Volume Number | 17 |
| Issue Number | 5 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-10-01 |
| Publisher Place | U.S.A. |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Production Fabrication Workstations Job shop scheduling Application specific integrated circuits Industrial engineering Semiconductor device modeling Circuit simulation Electrical equipment industry Companies |
| Content Type | Text |
| Resource Type | Article |
| Subject | Control and Systems Engineering Electrical and Electronic Engineering |
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