NDLI: Low-power and high-speed ROM modules for ASIC applications

Content Provider	IEEE Xplore Digital Library
Author	Ching-Rong Chang Jinn-Shyan Wang Cheng-Hui Yang
Copyright Year	1966
Abstract	We describe in this paper the design of a set of low-power and high-speed NOR-type ROM modules suitable for embedded applications in ASICs or SOCs. The circuit is derived from the four-phase high-speed precharge-discharge dynamic CMOS logic (NHS-PDCMOS) with the number of operational phases reduced from four to one. This facilitates the interconnections to other system blocks that are usually designed to be one phase. Experimental results show that for the size of 2K/spl times/8, the proposed high-speed ROM module is about 1.89 times faster, consumes 21% less power, and occupies similar silicon area as compared to a conventional design. Also for the same size, the proposed low-power ROM module is 1.17 times faster, 14% smaller, and consumes 83% less power as compared to the conventional design.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1516
Ending Page	1523
Page Count	8
File Size	297160
File Format	PDF
ISSN	00189200
Volume Number	36
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read only memory Application specific integrated circuits CMOS logic circuits Decoding CMOS process MOSFETs Integrated circuit interconnections Power system interconnection Voltage Logic circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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