NDLI: 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s

Content Provider	IEEE Xplore Digital Library
Author	Promitzer, G.
Copyright Year	1966
Abstract	Based on a conventional successive approximation ADC architecture, a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. A switching circuit is implemented to allow a wider input voltage range of the ADC. Together with a self-timed comparator, the power consumption is noticeably reduced while at the same time the sampling rate is doubled. Smaller input and reference capacitances reduce the requirements on the input and reference sources, respectively. Additionally, a widely clock-duty-cycle-independent control logic improves the applicability of the converter cell, especially for systems on chip. Results of measurements confirm the theoretical improvements.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1138
Ending Page	1143
Page Count	6
File Size	148000
File Format	PDF
ISSN	00189200
Volume Number	36
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Switching circuits Voltage Energy consumption Sampling methods Capacitance Clocks Control systems Logic System-on-a-chip
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC

A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-/spl mu/m CMOS

A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of $V_{text{IN}}/{2^N}$ for a Wide Range of Input and Output Voltages

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s

Similar Documents

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC

A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-/spl mu/m CMOS

A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of $V_{text{IN}}/{2^N}$ for a Wide Range of Input and Output Voltages

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s