NDLI: An architecture and implementation of MPEG audio layer III decoder using dual-core DSP

Content Provider	IEEE Xplore Digital Library
Author	Kyu Ha Lee Keun-Sup Lee Tae-Hoon Hwang Young-Cheol Park Dae Hee Youn
Copyright Year	1975
Abstract	A new architecture for the MP3 decoding system is proposed and implemented. The proposed system is based on a processor employing a dual-core (DSP and RISC) architecture. The MP3 decoding algorithm is implemented using the DSP core with high accuracy, and the RISC core performs bitstream buffering and system control in conjunction with a user interface. The system with this configuration can support an efficient parallel processing between DSP and RISC cores, so that it is possible to minimize the computational overhead. The implemented system employs a flash memory card for the storage, and it has a file management system that is compatible with PC. Also, it supports all sampling rates and data rates specified in MPEG-1/2 standards. The MP3 decoder developed is suitable for portable communication devices such as cellular telephones since it features high audio quality, low-power consumption and cost effectiveness.
Sponsorship	IEEE Consumer Electronics Society
Starting Page	928
Ending Page	933
Page Count	6
File Size	683807
File Format	PDF
ISSN	00983063
Volume Number	47
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Digital audio players Digital signal processing Reduced instruction set computing Control systems User interfaces Parallel processing Concurrent computing Flash memory Sampling methods
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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