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Design of self-checking fully differential circuits and boards

Content Provider	IEEE Xplore Digital Library
Author	Lubaszewski, M. Mir, S. Kolarik, V. Nielsen, C. Courtois, B.
Copyright Year	1993
Abstract	A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	113
Ending Page	128
Page Count	16
File Size	429743
File Format	PDF
ISSN	10638210
Volume Number	8
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Filters Design methodology Circuit faults Automatic testing Monitoring Clocks Frequency Narrowband Signal design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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