NDLI: A CMOS pulse-shrinking delay element for time interval measurement

Content Provider	IEEE Xplore Digital Library
Author	Chen, P. Shen-Luan Liu Jingshown Wu
Copyright Year	1992
Abstract	A deep sub-nanosecond resolved CMOS pulse-shrinking delay element used in the time-to-digital converter (TDC) is proposed. The pulse shrinking capability of the element is controlled by the dimension ratio of the adjacent gates. This control mechanism is completely different from the bias adjustment adopted in the conventional pulse-shrinking element. Without the need of continuous calibration, the presented element possesses not only extremely fine resolution, small single-shot errors, low power consumption, but also good insensitivity to the supply voltage variation. Being fabricated with 0.35 /spl mu/m CMOS technologies, the TDC made of the new elements has been measured to have a resolution of 68 ps. The effective resolution only varies 1.5 ps for a rather large supply voltage range from 3.5 to 4.5 V. The size of the circuit is 0.35 mm/spl times/0.09 mm only, excluding the I/O pads. Under a single 3.3-V power supply, the static power dissipation, including the I/O pads, is 1 /spl mu/W. The average power consumption is measured to be merely 1.2 mW under a measurement rate of 100 ksps.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	954
Ending Page	958
Page Count	5
File Size	231268
File Format	PDF
ISSN	10577130
Volume Number	47
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse measurements Delay effects Time measurement Energy consumption Voltage CMOS technology Power measurement Calibration Circuits Power supplies
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in