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Content Provider | IEEE Xplore Digital Library |
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Author | Dahlen, E. Gustin, J. Meredith, S. Moran, O. |
Copyright Year | 1981 |
Abstract | Designing a chip set for a new processor architecture like the IA-64 requires handling multiple aspects. They include implementing the processor interface; providing sufficient I/O bandwidth for servers; supporting accelerated graphics port (AGP) graphics; and providing sufficient memory bandwidth for the processor, I/O, and graphics. This article provides an introduction to the memory, I/O, and graphics subsystems of Intel's Itanium processor chip set and discusses several aspects of the processor bus. |
Sponsorship | IEEE Computer Society |
Starting Page | 69 |
Ending Page | 75 |
Page Count | 7 |
File Size | 91254 |
File Format | |
ISSN | 02721732 |
Volume Number | 20 |
Issue Number | 6 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2000-11-01 |
Publisher Place | U.S.A. |
Access Restriction | One Nation One Subscription (ONOS) |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Workstations Bridges Control systems Communication system control Graphics Read-write memory Random access memory Computer buffers Microprogramming Pins |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering Software Hardware and Architecture |
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