NDLI: EPIC: Explicitly Parallel Instruction Computing

Content Provider	IEEE Xplore Digital Library
Author	Schlansker, M.S. Rau, B.R.
Copyright Year	1970
Abstract	Over the past two and a half decades, the computer industry has grown accustomed to the spectacular rate of increase in microprocessor performance. The industry accomplished this without fundamentally rewriting programs in parallel form, without changing algorithms or languages, and often without even recompiling programs. Instruction level parallel processing achieves high performance without major changes to software. However, computers have thus far achieved this goal at the expense of tremendous hardware complexity-a complexity that has grown so large as to challenge the industry's ability to deliver ever-higher performance. The authors developed the Explicitly Parallel Instruction Computing (EPIC) style of architecture to enable higher levels of instruction-level-parallelism without unacceptable hardware complexity. They focus on the broader concept of EPIC as embodied by HPL-PD (formerly known as HPL PlayDoh) architecture, which encompasses a large space of possible EPIC ISAs (instruction set architectures). In this article, the authors focus on HPL-PD because it represents the essence of the EPIC philosophy while avoiding the idiosyncracies of a specific ISA.
Sponsorship	IEEE Computer Society
Starting Page	37
Ending Page	45
Page Count	9
File Size	183062
File Format	PDF
ISSN	00189162
Volume Number	33
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer aided instruction Concurrent computing Parallel processing Computer architecture Hardware VLIW Instruction sets Computer industry Circuits Application software
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Predicated switching - optimizing speculation on EPIC machines

An architectural framework for supporting heterogeneous instruction-set architectures

Toward advanced parallel processing: exploiting parallelism at task and instruction levels

HARP: a VLIW RISC processor

Extending Unix for scalable computing

A scalable parallel computational core for embedded processing

Simple-VLIW: A fundamental VLIW architectural simulation platform

Extracting speedup from C-code with poor instruction-level parallelism

Strategies for mapping algorithms to mediaprocessors for high performance

EPIC: Explicitly Parallel Instruction Computing

Similar Documents

Predicated switching - optimizing speculation on EPIC machines

An architectural framework for supporting heterogeneous instruction-set architectures

Toward advanced parallel processing: exploiting parallelism at task and instruction levels

HARP: a VLIW RISC processor

Extending Unix for scalable computing

A scalable parallel computational core for embedded processing

Simple-VLIW: A fundamental VLIW architectural simulation platform

Extracting speedup from C-code with poor instruction-level parallelism

Strategies for mapping algorithms to mediaprocessors for high performance

EPIC: Explicitly Parallel Instruction Computing