NDLI: Test generation for linear time-invariant analog circuits

Content Provider	IEEE Xplore Digital Library
Author	Chen-Yang Pan Kwang-Ting Cheng
Copyright Year	1992
Abstract	In this paper, we propose a cost-effective test generation technique for linear time-invariant analog circuits subject to the parametric faults. This technique requires only a small number of test patterns, as opposed to traditional functional testing which utilizes complex stimuli, to classify the circuits. We formulate the test-generation problem as a problem of deriving hyperplanes in the multidimensional space formed by a set of parameters of the device under test (DUT). These hyperplanes define the acceptance region in the measurement space and can be derived by a search-based heuristic. The coefficients of the hyperplanes are then used as test patterns for classification (to determine whether the DUT is in the acceptance region or not). A more general case of using arbitrary "linearly independent" test sequence for classification is also discussed. Experimental results show that less than 10% of misclassification can be achieved by a very small number of tests.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	554
Ending Page	564
Page Count	11
File Size	288009
File Format	PDF
ISSN	10577130
Volume Number	46
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Analog circuits Circuit faults Test equipment Electrical fault detection System testing Multidimensional systems Mixed analog digital integrated circuits Integrated circuit testing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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