NDLI: Optimal FPGA mapping and retiming with efficient initial state computation

Content Provider	IEEE Xplore Digital Library
Author	Cong, J. Chang Wu
Copyright Year	1982
Abstract	For sequential circuits with given initial states, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper, we present a novel polynomial time algorithm for optimal field programmable gate array (FPGA) mapping with forward retiming to minimize the clock period with efficient initial state computation. It considers forward retiming, initial state computation and mapping simultaneously. Our algorithm enables a new methodology of separating forward retiming from backward retiming. Since we guarantee to compute an optimal mapping with forward retiming solution, backward retiming can be performed as a preprocessing to try to push flip-flops (FFs) to primary inputs with consideration of only initial state computation. Thus, we can avoid the time-consuming iterations between retiming for clock period minimization and initial state computation. This algorithm compares very favorably to both conventional approaches of mapping followed by separate retiming and recent approaches of combined mapping with retiming, but without consideration of initial state computation. Our results show that our algorithm can reduce the clock period by 17.5% over conventional approaches of separate mapping with retiming. On the other hand, our algorithm can guarantee efficient initial state computation in the mapped and retimed circuits with only 2.8% increase in clock period over the optimal mapping with general retiming solutions, while the initial state computation for the latter solutions may need prohibitively long runtime for designs with over several hundred FFs.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1595
Ending Page	1607
Page Count	13
File Size	503284
File Format	PDF
ISSN	02780070
Volume Number	18
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Clocks Sequential circuits Polynomials Simultaneous localization and mapping Data preprocessing Flip-flops Minimization Runtime Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

On retiming for FPGA logic module minimization

An efficient algorithm for performance-optimal FPGA technology mapping with retiming

Optimal FPGA mapping and retiming with efficient initial state computation

Wire Retiming Problem With Net Topology Optimization

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

FPGA module minimization

Generic ILP-based approaches for time-multiplexed FPGA partitioning

Optimal clock period FPGA technology mapping for sequential circuits

Minimum-area sequential budgeting for FPGA

Optimal FPGA mapping and retiming with efficient initial state computation

Similar Documents

On retiming for FPGA logic module minimization

An efficient algorithm for performance-optimal FPGA technology mapping with retiming

Optimal FPGA mapping and retiming with efficient initial state computation

Wire Retiming Problem With Net Topology Optimization

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

FPGA module minimization

Generic ILP-based approaches for time-multiplexed FPGA partitioning

Optimal clock period FPGA technology mapping for sequential circuits

Minimum-area sequential budgeting for FPGA

Optimal FPGA mapping and retiming with efficient initial state computation