NDLI: Fractal engine: an affine video processor core for multimedia applications

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Fractal engine: an affine video processor core for multimedia applications

Content Provider	IEEE Xplore Digital Library
Author	Fatemi, O. Panchanathan, S.P.
Copyright Year	1991
Abstract	The advances in VLSI technology, high-speed processor designs, Internet/Intranet implementations, broadband networks (ATM and ISDN), and compression standards (JPEG, MPEG, H.261, H.263, and G.273) are leading to the popularity of multimedia applications. Examples include video over the Internet, interactive TV, distance learning, telemedicine, and digital libraries. Visual media processing poses challenges from several perspectives, specifically from the points of view of real-time implementation and scalability. We first present an overview and categorization of the various architectural approaches for multimedia processing. The fundamental operations involved in a majority of visual processing tasks are then derived. We propose an affine transform-processor-core-based video processor architecture called the fractal engine that is capable of implementing the basic visual processing operations. The fractal engine is an open architecture, and is designed to be modular and scalable, and therefore has the potential to satisfy the heterogeneous computing requirements of the different media types in multimedia processing. Details of the individual modules of the fractal engine as well the implementation of the architecture in VHDL are also presented.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	892
Ending Page	908
Page Count	17
File Size	411662
File Format	PDF
ISSN	10518215
Volume Number	8
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fractals Search engines Computer architecture Video compression Transform coding Very large scale integration Process design IP networks Broadband communication ISDN
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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