NDLI: A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing

Content Provider	IEEE Xplore Digital Library
Author	Berger, R. Lyons, W.G. Soares, A.
Copyright Year	1966
Abstract	A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-/spl mu/m drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1259
Ending Page	1261
Page Count	3
File Size	55595
File Format	PDF
ISSN	00189200
Volume Number	33
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Clocks Performance evaluation CMOS process Digital filters Filtering Wideband Spectral analysis Digital signal processing chips Pulse circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 20-ns CMOS micro DSP core for video-signal processing

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

The architectures and design of a 20-MHz real-time DSP chip set

Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS

A four-channel CMOS codec filter circuit SICOFI-4

A High Quality Digital TV Utilizing 2 CMOS Chips

High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

A single-chip video-processing IC made by an improved Bi-CMOS process

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing

Similar Documents

A 20-ns CMOS micro DSP core for video-signal processing

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

The architectures and design of a 20-MHz real-time DSP chip set

Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS

A four-channel CMOS codec filter circuit SICOFI-4

A High Quality Digital TV Utilizing 2 CMOS Chips

High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

A single-chip video-processing IC made by an improved Bi-CMOS process

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing