NDLI: Design of a high-speed square generator

Content Provider	IEEE Xplore Digital Library
Author	Chin-Long Wey Ming-Der Shieh
Copyright Year	1968
Abstract	Given a binary number N, the simplest way for evaluating its square N/sup 2/ is the use of ROM look-up tables. For example, the squares of 12-bit numbers can be stored in a ROM of (2/sup 12//spl times/24) bits, which takes an area of 3.5 mm/sup 2/ and an access time of 9.96 ns with 0.8 /spl mu/m CMOS process. However, the conventional ROM table approaches are limited only for small bit size applications due to the unmanageable increase of the ROM table size. A novel design of square generator circuit using a folding approach is presented for high speed performance applications. Results show that, with the same process, the proposed square generator circuit takes 12.27 ns to generate the squares of 40 bit numbers with an area of about 2.88 times that of the (2/sup 12//spl times/24) ROM, i.e., 10 mm/sup 2/ a design trade-off between speed and area. A nested structure is also presented to achieve a 103 bit square generator with a delay of 15.82 ns. The bit size can be further increased by adding more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit size and high speed applications.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	1021
Ending Page	1026
Page Count	6
File Size	258998
File Format	PDF
ISSN	00189340
Volume Number	47
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read only memory Table lookup Circuits CMOS process Delay Signal generators Digital signal processing Image processing System performance Computer architecture
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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