NDLI: A low voltage SONOS nonvolatile semiconductor memory technology

Content Provider	IEEE Xplore Digital Library
Author	White, M.H. Yang Yang Ansha Purwar French, M.L.
Copyright Year	1994
Abstract	The triple-dielectric polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E/sup 2/PROMs suitable for semiconductor disks and as a replacement for high-density dynamic random access memories (DRAMs). Low programming voltages (5 V) and high endurance (greater than 10/sup 7/ cycles) are possible in this multidielectric technology as the intermediate Si/sub 3/N/sub 4/ layer is scaled to thicknesses of 50 /spl Aring/. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and associated complementary metal-oxide-semiconductor (CMOS) peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F/sup 2/ where F is the technology feature size. A 0.20 /spl mu/m feature size permits a 1TC area of 0.24 /spl mu/m/sup 2/ for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.
Sponsorship	Ericsson IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	190
Ending Page	195
Page Count	6
File Size	143881
File Format	PDF
ISSN	10709886
Volume Number	20
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-06-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage SONOS devices Nonvolatile memory Semiconductor memory CMOS technology PROM DRAM chips Dynamic voltage scaling Insulation Metal-insulator structures
Content Type	Text
Resource Type	Article
Subject	Engineering

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