NDLI: Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Please wait, while we are loading the content...

Limitation of the TiN/Ti layer formed by the rapid thermal heat treatment of pure Ti films in an NH/sub 3/ ambient in fabrication of submicrometer CMOS flash EPROM IC's

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

An overview of level set methods for etching, deposition, and lithography development

Modeling the effect of hot lots in semiconductor manufacturing systems

Year : 1996 Volume : 9

Year : 1995 Volume : 8

Year : 1994 Volume : 7

Year : 1993 Volume : 6

Year : 1992 Volume : 5

Year : 1991 Volume : 4

Year : 1990 Volume : 3

Year : 1989 Volume : 2

Year : 1988 Volume : 1

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Content Provider	IEEE Xplore Digital Library
Author	Friedmann, J.B. Shohet, J.L. Mau, R. Hershkowitz, N. Bisgaard, S. Shawming Ma McVittie, J.P.
Copyright Year	1988
Abstract	In this work, the effects of plasma-parameter variations on the charging damage of polysilicon-gate MOS capacitor test structures exposed to O/sub 2/ electron-cyclotron-resonance (ECR) plasmas are investigated. The results show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities.
Sponsorship	IEEE Electron Devices Society IEEE Components, Packaging, and Manufacturing Technology Society IEEE Reliability Society IEEE Solid-State Circuits Society
Starting Page	154
Ending Page	166
Page Count	13
File Size	587273
File Format	PDF
ISSN	08946507
Volume Number	10
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Plasma measurements Testing Plasma materials processing Plasma devices Electrodes MOS capacitors Electric breakdown Probes Electrons Semiconductor device modeling
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Thin-oxide damage from gate charging during plasma processing

Modeling oxide thickness dependence of charging damage by plasma processing

Modeling of oxide breakdown from gate charging during resist ashing

Effects of wafer temperature on plasma charging induced damage to MOS gate oxide

Prediction of plasma charging induced gate oxide damage by plasma charging probe

Oxide damage from plasma charging: breakdown mechanism and oxide quality

Plasma charging damage on MOS devices with gate insulator of high-dielectric constant material

Sensitivity and limitations of plasma charging damage measurements using MOS capacitors structures

A model and experiments for thin oxide damage from wafer charging in magnetron plasmas

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Similar Documents

Thin-oxide damage from gate charging during plasma processing

Modeling oxide thickness dependence of charging damage by plasma processing

Modeling of oxide breakdown from gate charging during resist ashing

Effects of wafer temperature on plasma charging induced damage to MOS gate oxide

Prediction of plasma charging induced gate oxide damage by plasma charging probe

Oxide damage from plasma charging: breakdown mechanism and oxide quality

Plasma charging damage on MOS devices with gate insulator of high-dielectric constant material

Sensitivity and limitations of plasma charging damage measurements using MOS capacitors structures

A model and experiments for thin oxide damage from wafer charging in magnetron plasmas

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing