NDLI: Performance analysis and tuning for a single-chip multiprocessor DSP

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Performance analysis and tuning for a single-chip multiprocessor DSP

Content Provider	IEEE Xplore Digital Library
Author	Jihong Kim Yongmin Kim
Copyright Year	1997
Abstract	A new generation of high performance programmable digital signal processors has a highly integrated parallel architecture, incorporating special purpose hardware features, on-chip memory, and multiple processors into a single chip. Such single chip multiprocessor DSPs, however, require a sophisticated performance monitoring tool to achieve maximum performance. The authors discuss the requirements and functionality of performance monitoring tools suitable for single chip multiprocessor DSPs. Specifically, they describe a performance monitoring tool that satisfies these requirements and functionality: the MVP Performance Monitor, developed for the Texas Instruments' TMS320C80 Multimedia Video Processor. They present an overview of the MPM and a general performance tuning approach using the MPM. An 8/spl times/8 block based 2D discrete cosine transform (DCT) implementation demonstrates the MPM's effectiveness. The authors achieved an overall speedup of 4.67 by tuning the performance based on the monitoring results from the MPM.
Starting Page	68
Ending Page	79
Page Count	12
File Size	278020
File Format	PDF
ISSN	10923063
Volume Number	5
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Digital signal processing Monitoring Hardware Application software Instruments Digital signal processing chips System software Counting circuits Parallel architectures
Content Type	Text
Resource Type	Article
Subject	Engineering

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