NDLI: An area effective 1-chip QAM LSI for digital CATV

Content Provider	IEEE Xplore Digital Library
Author	Fukuoka, T. Nakai, Y. Hayashi, D. Hayashi, T. Soga, S. Fukuda, K. Nakakura, Y.
Copyright Year	1975
Abstract	We have developed a single, standard cell LSI equipped with a QAM (quadrature amplitude modulation) demodulator, a FEC (forward error correction) decoder, and AD/DA converters. The most important features of our LSI are its very small area and low power. In addition, this design can be used as a core module in an LSI library. The QAM demodulator has four modes of operations: 4, 16, 32, and 64 mode. The QAM demodulation is performed entirely in the digital domain. The FEC decoder includes frame synchronization, convolutional deinterleaving, RS (Reed-Solomon) decoding, and descrambling. We have achieved a small area and low power by using the following three methods. First, we adopted an ESGDD (enhanced stop & go decision-directed) algorithm as an AFC (automatic frequency control)/APC (automatic phase control) algorithm. The ESGDD algorithm which we developed based on the SGDD (stop & go decision-directed) algorithm which is a modified LMS (least mean square) algorithm, that is generally used for equalization. This new algorithm does not need an NCO (numerically controlled oscillator) operation which is usually indispensable when performing the AFC/APC algorithm. Next, we took advantage of the SGDD algorithm's sub-sampling method to perform equalization. This method can reduce the amount of the equalizing calculation. Finally, we optimized the EAB (Euclid algorithm block) in the RS decoding block, which lead to the reduction needed to perform the number of steps of the RS decoding.
Sponsorship	IEEE Consumer Electronics Society
Starting Page	649
Ending Page	654
Page Count	6
File Size	622917
File Format	PDF
ISSN	00983063
Volume Number	43
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Quadrature amplitude modulation Large scale integration Decoding Demodulation Forward error correction Automatic frequency control Standards development Software libraries Frequency synchronization Reed-Solomon codes
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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