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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chingwei Yeh Chi-Shong Wang |
| Copyright Year | 1982 |
| Abstract | Rectilinear placement is an important process for mixed macro block/standard cells design due to frequent presence of preplaced macro blocks. A prevailing solution to this problem is to divide the rectilinear region into rectangular sub-regions and partition cells into these sub-regions before applying standard placement algorithms. For such a strategy to work, the partitioning objective must closely correlate with the global routing objective. In this paper, we propose a new method to integrate global routing with partitioning. The salient features of our approach consist of (1) a new edge cost model and its computation using an incremental assignment technique; (2) a resistive network analogy for net cost modeling and a randomized algorithm for resistance computation; (3) a robust partitioning framework that combines the ideas of (1) and (2). Also, a dynamic strategy is proposed to evaluate the performance of the algorithm. Our method has been tested on several benchmark circuits and displayed excellent results in terms of both wire length and routability. |
| Sponsorship | IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society |
| Starting Page | 83 |
| Ending Page | 91 |
| Page Count | 9 |
| File Size | 1046813 |
| File Format | |
| ISSN | 02780070 |
| Volume Number | 15 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Partitioning algorithms Costs Computer networks Circuit testing Computational modeling Robustness Benchmark testing Wire Process planning |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software |
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