NDLI: Fully parallel integrated CAM/RAM using preclassification to enable large capacities

Content Provider	IEEE Xplore Digital Library
Author	Schultz, K.J. Gulak, P.G.
Copyright Year	1966
Abstract	Many applications would benefit from the availability of large-capacity content addressable memories (CAMs). However, while RAMs, EEPROMs, and other memory types achieve ever-increasing per-chip bit counts, CAMs show little promise of following suit, due primarily to an inherent difficulty in implementing two-dimensional decoding. The serialized operation of most proposed solutions is not acceptable in speed-sensitive environments. In response to the resulting need, this paper describes a fully-parallel (single-clock-cycle) CAM architecture that uses the concept of "preclassification" to realize a second dimension of decoding without compromising throughput. As is typically the case, each CAM entry is used as an index to additional data in a RAM. To achieve improved system integration, the preclassified CAM is merged into the same physical array as its target RAM, and both use the same core cells. Architecture and operation of the resulting novel memory are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. The memory circuits, designed in 0.8 /spl mu/m BiCMOS technology, may be employed in chips as large as 1 Mb, and simulations confirm 37 MHz operation for this capacity. To experimentally verify the feasibility of the architectural and circuit design, an 8 kb test chip was fabricated and found to be fully functional at clock speeds up to 59 MHz, with a power dissipation of 260 mW at 50 MHz.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	689
Ending Page	699
Page Count	11
File Size	1402275
File Format	PDF
ISSN	00189200
Volume Number	31
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer aided manufacturing CADCAM Read-write memory Random access memory Decoding Circuit testing Associative memory EPROM Throughput BiCMOS integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Integrated-circuit content-addressable memories

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

A circuit design of intelligent cache DRAM with automatic write-back capability

A CAM with mixed serial-parallel comparison for use in low energy caches

A content addressable memory with a fault-tolerance mechanism

A content-addressable memory cell with MNOS transistors

BiCMOS circuit technology for a high-speed SRAM

A high-speed string-search engine

A self-testing reconfigurable CAM

Fully parallel integrated CAM/RAM using preclassification to enable large capacities

Similar Documents

Integrated-circuit content-addressable memories

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

A circuit design of intelligent cache DRAM with automatic write-back capability

A CAM with mixed serial-parallel comparison for use in low energy caches

A content addressable memory with a fault-tolerance mechanism

A content-addressable memory cell with MNOS transistors

BiCMOS circuit technology for a high-speed SRAM

A high-speed string-search engine

A self-testing reconfigurable CAM

Fully parallel integrated CAM/RAM using preclassification to enable large capacities