NDLI: Fault-tolerant designs for 256 Mb DRAM

Content Provider	IEEE Xplore Digital Library
Author	Kirihata, T. Watanabe, Y. Hing Wong DeBrosse, J.K. Yoshida, M. Kato, D. Fujii, S. Wordeman, M.R. Poechmueller, P. Parke, S.A. Asao, Y.
Copyright Year	1966
Abstract	This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm/sup 2/ 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 /spl mu/A per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	558
Ending Page	566
Page Count	9
File Size	2366760
File Format	PDF
ISSN	00189200
Volume Number	31
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Random access memory Circuit faults Redundancy Research and development Costs Data compression MOS devices Hardware Computational modeling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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