NDLI: Communication-free data allocation techniques for parallelizing compilers on multicomputers

Content Provider	IEEE Xplore Digital Library
Author	Tzung-Shi Chen Jang-Ping Sheu
Copyright Year	1990
Abstract	In distributed memory multicomputers, local memory accesses are much faster than those involving interprocessor communication. For the sake of reducing or even eliminating the interprocessor communication, the array elements in programs must be carefully distributed to local memory of processors for parallel execution. We devote our efforts to the techniques of allocating array elements of nested loops onto multicomputers in a communication-free fashion for parallelizing compilers. We first analyze the pattern of references among all arrays referenced by a nested loop, and then partition the iteration space into blocks without interblock communication. The arrays can be partitioned under the communication-free criteria with nonduplicate or duplicate data. Finally, a heuristic method for mapping the partitioned array elements and iterations onto the fixed-size multicomputers under the consideration of load balancing is proposed. Based on these methods, the nested loops can execute without any communication overhead on the distributed memory multicomputers. Moreover, the performance of the strategies with nonduplicate and duplicate data for matrix multiplication is studied.<>
Sponsorship	IEEE Computer Society
Starting Page	924
Ending Page	938
Page Count	15
File Size	1595343
File Format	PDF
ISSN	10459219
Volume Number	5
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Program processors Random access memory Data mining Parallel machines Pattern analysis Load management Councils Computer science Magnetic heads
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computational Theory and Mathematics Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers

Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers

A framework for exploiting task and data parallelism on distributed memory multicomputers

A linear algebra framework for automatic determination of optimal data layouts

Compile-time techniques for data distribution in distributed memory machines

A compiler optimization algorithm for shared-memory multiprocessors

Data dependence testing in practice

Compiling for distributed memory architectures

A graph based framework to detect optimal memory layouts for improving data locality

Communication-free data allocation techniques for parallelizing compilers on multicomputers

Similar Documents

Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers

Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers

A framework for exploiting task and data parallelism on distributed memory multicomputers

A linear algebra framework for automatic determination of optimal data layouts

Compile-time techniques for data distribution in distributed memory machines

A compiler optimization algorithm for shared-memory multiprocessors

Data dependence testing in practice

Compiling for distributed memory architectures

A graph based framework to detect optimal memory layouts for improving data locality

Communication-free data allocation techniques for parallelizing compilers on multicomputers