NDLI: Timing constraints for wave-pipelined systems

Content Provider	IEEE Xplore Digital Library
Author	Gray, C.T. Liu, W. Cavin III, R.K.
Copyright Year	1982
Abstract	Wave-pipelining is a timing methodology used in digital systems to achieve maximal rate operation. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic and maximizing the utilization of the logic without inserting registers. This paper presents a timing constraint formulation for the correct clocking of wave-pipelined systems. Both single- and multiple-stage systems including feedback are considered. Based on the formulation of this paper, several important new results are presented relating to performance limits of wave-pipelined circuits. These results include the specification of distinct and disjoint regions of valid operation dependent on the clock period, intentional clock skew, and the global clock latency. Also, implications and motivations for the use of accurate delay models and exact timing analysis in the determination of combinational logic delays are given, and an analogous relationship between the multi-stage system and the single-stage system in terms of performance limits is shown. The minimum clock period is obtained by clock skew optimization formulated as a linear program. In addition, important special cases are examined and their relative performance limits are analyzed.<>
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	987
Ending Page	1004
Page Count	18
File Size	1563130
File Format	PDF
ISSN	02780070
Volume Number	13
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Clocks Logic Delay Performance analysis Digital systems Pipeline processing Registers Feedback Circuits
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

Clock period minimization with wave pipelining

Integrated parametric timing optimization of digital systems

Optimal retiming of level-clocked circuits using symmetric clock schedules

Synchronization of wave-pipelined circuits

Surfing Pipelines: Theory and Implementation

Clocking for correct functionality on wave pipelined circuits

Retiming and clock scheduling for digital circuit optimization

Performance analysis and optimization of mixed asynchronous synchronous systems

Timing constraints for wave-pipelined systems

Similar Documents

Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

Clock period minimization with wave pipelining

Integrated parametric timing optimization of digital systems

Optimal retiming of level-clocked circuits using symmetric clock schedules

Synchronization of wave-pipelined circuits

Surfing Pipelines: Theory and Implementation

Clocking for correct functionality on wave pipelined circuits

Retiming and clock scheduling for digital circuit optimization

Performance analysis and optimization of mixed asynchronous synchronous systems

Timing constraints for wave-pipelined systems