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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Maneatis, J.G. Horowitz, M.A. |
| Copyright Year | 1966 |
| Abstract | A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay resolution equal to a buffer delay divided by the number of rings. The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay. The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages. Experimental results from a 2- mu m N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps.< |
| Sponsorship | IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE |
| Starting Page | 1273 |
| Ending Page | 1282 |
| Page Count | 10 |
| File Size | 1060800 |
| File Format | |
| ISSN | 00189200 |
| Volume Number | 28 |
| Issue Number | 12 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-12-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Ring oscillators Circuit testing Integrated circuit testing Phased arrays Frequency Low voltage Voltage-controlled oscillators Clocks Integrated circuit technology |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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