NDLI: Evaluation of a three-dimensional memory cube system

Content Provider	IEEE Xplore Digital Library
Author	Bertin, C.L. Perlman, D.J. Shanken, S.N.
Copyright Year	1978
Abstract	Silicon cubes consisting of 18-20 1-Mb DRAM chips have been fabricated. In the stacking process, the chips are joined by adhesive to form the cube, interconnected by chip metallization processes, and packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1-Mb DRAM memory modules that normally form the card array. Memory tube operation is verified by testing both original and cube memory cards on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines, and PGA substrate were performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines.<>
Sponsorship	IEEE Electronic Industries Alliance American Society of Mechanical Engineering (ASME) NBS SAE
Starting Page	1006
Ending Page	1011
Page Count	6
File Size	603290
File Format	PDF
ISSN	01486411
Volume Number	16
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-12-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Electronics packaging Circuit testing Silicon Stacking Metallization Ceramics Random access memory Circuit simulation Wiring
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Engineering Electrical and Electronic Engineering

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