NDLI: A VLSI neural processor for image data compression using self-organization networks

Content Provider	IEEE Xplore Digital Library
Author	Fang, W.-C. Sheu, B.J. Chen, O.T.-C. Choi, J.
Copyright Year	1990
Abstract	An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mm*6.8 mm in a 2.0 mu m scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.<>
Sponsorship	IEEE Computational Intelligence Society
Starting Page	506
Ending Page	518
Page Count	13
File Size	1381472
File Format	PDF
ISSN	10459227
Volume Number	3
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Data compression Circuit testing Neural networks CMOS technology Adaptive systems Image coding Frequency Vector quantization Analog computers
Content Type	Text
Resource Type	Article
Subject	Artificial Intelligence Computer Networks and Communications Computer Science Applications Software

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