NDLI: A video digital signal processor with a vector-pipeline architecture

Content Provider	IEEE Xplore Digital Library
Author	Aono, K. Toyokura, M. Araki, T. Ohtani, A. Kodama, H. Okamoto, K.
Copyright Year	1966
Abstract	A 2-GOPS, 60-MIPS DSP with a new vector-pipeline architecture (VDSP: vector digital signal processor) has been developed for video CODEC systems, using 0.8- mu m CMOS technology. The VDSP is programmable and can be adapted to handle various standards for video coding, such as those of CCITT H.261, MPEG (Moving Picture Experts Group), and JPEG (Joint Photographic Experts Group). It also contains a discrete cosine transform (DCT) core as one of the special processing units used to enhance performance. The 12.38-mm*12.90-mm VDSP, which consists of approximately 930 K transistors, operates at a maximum clock rate of 60 MHz. The encoder and the decoder specified in CCITT H.261 (full-CIF mode at 15 frames/s or more, 64 kb/s) can be realized with only two VDSP chips and only one VDSP chip, respectively.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1886
Ending Page	1894
Page Count	9
File Size	873685
File Format	PDF
ISSN	00189200
Volume Number	27
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processors CMOS technology Discrete cosine transforms Digital signal processing Video codecs CMOS process Video coding MPEG standards Clocks Decoding
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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