NDLI: Reduction of oxide charge and interface-trap density in MOS capacitors with ITO gates

Content Provider	IEEE Xplore Digital Library
Author	Weijtens, C.H.L.
Copyright Year	1963
Abstract	The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N/sub f/ and N/sub it/, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240 degrees C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950 degrees C in N/sub 2/, followed by a 30 min anneal in N/sub 2//20% H/sub 2/ at 450 degrees C. Typical values obtained for N/sub it/ and N/sub f/ are 4.210/sup 10/ cm/sup -2/ and 2.810/sup 10/ cm/sup -2/, respectively. These values are further reduced to 1.9*10/sup 10/ cm/sup -2/ and >
Sponsorship	IEEE Electron Devices Society
Starting Page	1889
Ending Page	1894
Page Count	6
File Size	650597
File Format	PDF
ISSN	00189383
Volume Number	39
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOS capacitors Indium tin oxide Rapid thermal annealing Voltage Silicon Solid state circuits Charge coupled devices Insulation Capacitance measurement Current measurement
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors

New insights into radiation-induced oxide-trap charge through thermally-stimulated-current measurement and analysis (MOS capacitors)

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ and InP Capacitors

Radiation-Induced Hole Trapping and Interface State Characteristics of Al-Gate and Poly-Si Gate MOS Capacitors

Interface State Density of Single Vertical Nanowire MOS Capacitors

Indium out-diffusion from silicon during rapid thermal annealing

Effects of Bias on the Irradiation and Annealing Responses of 4H-SiC MOS Devices

A New Measurement Technique for MOS Capacitors

A charge-oriented model for MOS transistor capacitances

Reduction of oxide charge and interface-trap density in MOS capacitors with ITO gates

Similar Documents

Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors

New insights into radiation-induced oxide-trap charge through thermally-stimulated-current measurement and analysis (MOS capacitors)

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ and InP Capacitors

Radiation-Induced Hole Trapping and Interface State Characteristics of Al-Gate and Poly-Si Gate MOS Capacitors

Interface State Density of Single Vertical Nanowire MOS Capacitors

Indium out-diffusion from silicon during rapid thermal annealing

Effects of Bias on the Irradiation and Annealing Responses of 4H-SiC MOS Devices

A New Measurement Technique for MOS Capacitors

A charge-oriented model for MOS transistor capacitances

Reduction of oxide charge and interface-trap density in MOS capacitors with ITO gates