NDLI: A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

Content Provider	IEEE Xplore Digital Library
Author	Nakase, Y. Suda, K. Mashiko, K. Ikeda, T. Kayano, S.
Copyright Year	1966
Abstract	A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0* 10/sup 17/ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	518
Ending Page	524
Page Count	7
File Size	730052
File Format	PDF
ISSN	00189200
Volume Number	26
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Circuits Read-write memory Random access memory Isolation technology Transistors Energy consumption Writing Cache memory Control systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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