NDLI: Thin-film SOI CMOS transistors with p/sup +/-polysilicon gates

Content Provider	IEEE Xplore Digital Library
Author	Davis, J.R. Armstrong, G.A. Thomas, N.J. Doyle, A.
Copyright Year	1963
Abstract	A comparison is given of the use of p/sup +/-polysilicon and n/sup +/-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide.<>
Sponsorship	IEEE Electron Devices Society
Starting Page	32
Ending Page	38
Page Count	7
File Size	723035
File Format	PDF
ISSN	00189383
Volume Number	38
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors Silicon on insulator technology CMOS process Semiconductor films Substrates Numerical simulation Doping Voltage control Threshold voltage Electric breakdown
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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