NDLI: Square rooting algorithms for integer and floating-point numbers

Content Provider	IEEE Xplore Digital Library
Author	Hashemian, R.
Copyright Year	1968
Abstract	An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods.<>
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	1025
Ending Page	1029
Page Count	5
File Size	469807
File Format	PDF
ISSN	00189340
Volume Number	39
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Iterative algorithms Signal processing algorithms Arithmetic Image processing Partitioning algorithms Equations Computational modeling Error analysis Graphics Image edge detection
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reliable floating-point arithmetic algorithms for error-coded operands

Floating point fault tolerance with backward error assertions

Potential speedup using decimal floating-point hardware

Error-free solution to a Toeplitz system of equations

Faster floating-point square root for integer processors

A floating point pipeline CORDIC processor with extended operation set

A hybrid number system multiplier for graphics and complex arithmetic applications

Floating-point error analysis based on affine arithmetic

A Hardware/Software Co-design Architecture of Canny Edge Detection

Square rooting algorithms for integer and floating-point numbers

Similar Documents

Reliable floating-point arithmetic algorithms for error-coded operands

Floating point fault tolerance with backward error assertions

Potential speedup using decimal floating-point hardware

Error-free solution to a Toeplitz system of equations

Faster floating-point square root for integer processors

A floating point pipeline CORDIC processor with extended operation set

A hybrid number system multiplier for graphics and complex arithmetic applications

Floating-point error analysis based on affine arithmetic

A Hardware/Software Co-design Architecture of Canny Edge Detection

Square rooting algorithms for integer and floating-point numbers