NDLI: A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

Content Provider	IEEE Xplore Digital Library
Author	Arimoto, K. Fujishima, K. Matsuda, Y. Tsukude, M. Oishi, T. Wakamiya, W. Satoh, S. Yamada, M. Nakano, T.
Copyright Year	1966
Abstract	A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-line (TBL) array, includes suitable dummy and space word-line configurations which suppress the inter-bit-line noise and bring yield improvement. The multipurpose register (MPR) designed for the hierarchical data bus structure provides a line-mode test (LMT), copy write, and cache access capability. The LMT with on-chip test circuits using the MPR and a comparator creates a random test pattern and reduces the test time to 1/1000. A field shield isolation and a T-shaped stacked capacitor allow the layout of a 4.8- mu m/sup 2/ cell size with a storage capacitance of 35 fF. These techniques enable the 3.3-V 16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power dissipation at 120-ns cycle time.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1184
Ending Page	1190
Page Count	7
File Size	1013980
File Format	PDF
ISSN	00189200
Volume Number	24
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Circuit testing Power dissipation Dynamic voltage scaling Registers Capacitance Power supplies Noise reduction Maintenance Wiring
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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