NDLI: Development of a new self-aligning contact technology

Content Provider	IEEE Xplore Digital Library
Author	Lavery, J. Armstrong, M.B. Gamble, H.S.
Copyright Year	1963
Abstract	A self-aligning contact process (SACMOS) for MOS/VLSI technology is described. A new technique involving submerged implant into the source and drain is employed. This enables the enhanced oxidation of the previously heavily doped polysilicon gate compared to the more lightly doped source and drain. The implant also provides the source and drain extensions. During oxidation, silicon nitride pads protect all contacts. A noncritical masking and etching stage is used to yield contacts. The process uses two extra masking stages to produce self-aligned contacts to the source, drain, and gate of MOS transistors, yielding a significant reduction in the area required for contact regions and hence a greater packing density. A process verification chip illustrated that discrete transistors designed using the new process exhibited similar properties to conventionally designed devices. Also a 21-stage ring oscillator designed with a minimum dimension of 6 µm occupied 15 percent less space than a conventional device and operated at the same speed under similar bias conditions. Finally it is estimated that a ROM designed using the new process occupies 25 percent less space.
Sponsorship	IEEE Electron Devices Society
Starting Page	1039
Ending Page	1045
Page Count	7
File Size	1020628
File Format	PDF
ISSN	00189383
Volume Number	34
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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