NDLI: Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures

Content Provider	IEEE Xplore Digital Library
Author	Jing-Yang Jou Abraham, J.A.
Copyright Year	1963
Abstract	Hardware for executing matrix arithmetic and signal processing algorithms at high speeds is in great demand in many real-time and scientific applications. With the advent of VLSI technology, large numbers of processing elements which cooperate with each other at high speed have become economically feasible. Since any functional error in a high-performance system may seriously jeopardize the operation of the system and its data integrity, some level of fault tolerance must be incorporated in order to ensure that the results of long computations are valid. Since the major computational requirements for many important real-time signal processing tasks can be reduced to a common set of basic matrix operations, the development of a unified fault-tolerant scheme for matrix operations can solve the problems of both reliable signal processing and reliable matrix operations. Earlier work proposed a low-cost checksum scheme for fault-tolerant matrix operations on multiple processor systems. However, this scheme can only correct errors in matrix multiplication; it can detect, but not correct, errors in matrix-vector multiplication, LU decomposition, matrix inversion, etc. In order to solve these problems with the checksum scheme, a very general matrix encoding scheme is proposed in this paper to achieve fault-tolerant matrix arithmetic and signal processing with linear arrays, which are believed to hold the most promise in VLSI computing structures for their flexibility, low cost, and applicability to most of the interesting algorithms. This proposed technique is, therefore, a very cost-effective encoding technique to achieve fault-tolerant matrix arithmetic and signal processing on highly concurrent VLSI computing structures.
Sponsorship	IEEE Publication
Starting Page	732
Ending Page	741
Page Count	10
File Size	910067
File Format	PDF
ISSN	00189219
Volume Number	74
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Arithmetic Signal processing Concurrent computing Matrix decomposition Signal processing algorithms Very large scale integration Fault tolerant systems Error correction Encoding
Content Type	Text
Resource Type	Article
Subject	Computer Science Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy

Highly concurrent computing structures for matrix arithmetic and signal processing

Fault-tolerant VLSI processor array for the SVD

Modified residue codes based on residue number system as a fault tolerance scheme

Fault-tolerant computations over replicated finite rings

Fault Tolerance Techniques for Array Structures Used in Supercomputing

Evaluating reliability improvements of fault tolerant VLSI processor arrays

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors

Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures

Similar Documents

A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy

Highly concurrent computing structures for matrix arithmetic and signal processing

Fault-tolerant VLSI processor array for the SVD

Modified residue codes based on residue number system as a fault tolerance scheme

Fault-tolerant computations over replicated finite rings

Fault Tolerance Techniques for Array Structures Used in Supercomputing

Evaluating reliability improvements of fault tolerant VLSI processor arrays

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors

Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures