NDLI: Space-Time Domain Expansion Approach to VLSI and Its Application to Hierarchical Scene Matching

Content Provider	IEEE Xplore Digital Library
Author	Cheng, Heng-Da Lin, Wei-Chung Fu, King-Sun
Copyright Year	1979
Abstract	VLSI technology has recently received increasing attention due to its high performance and high reliability. Designing a VLSI structure systematically for a given task becomes a very important problem to many computer engineers. In this paper, we present a method to transform a recursive computation task into a VLSI structure systematically. The main advantages of this approach are its simplicity and completeness. Several examples, such as vector inner product, matrix multiplication, convolution, comparison operations in relational database and fast Fourier transformation (FFT), are given to demonstrate the transformation procedure. Finally, we apply the proposed method to hierarchical scene matching. Scene matching refers to the process of locating or matching a region of an image with a corresponding region of another view of the same image taken from a different viewing angle or at a different time. We first present a constant threshold estimation for hierarchical scene matching. The VLSI implementation of the hierarchical scene matching is then described in detail.
Sponsorship	IEEE Computer Society
Starting Page	306
Ending Page	319
Page Count	14
File Size	4645846
File Format	PDF
ISSN	01628828
Volume Number	PAMI-7
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Layout Space technology Convolution Relational databases Systolic arrays Application software Reliability engineering Design engineering VLSI technique Geometric transformation image pyramid intensity transformation sequential hierarchical scene matching space-time domain expansion threshold estimation
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Artificial Intelligence Computational Theory and Mathematics Computer Vision and Pattern Recognition Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A novel systolic array structure for DCT

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation

Sequential Hierarchical Scene Matching

Multirate VLSI arrays and their synthesis

A VLSI for real-time linear operations and transforms

Organization of Relational Models for Scene Analysis

Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform

Erratum: Implementation of convolution and Fourier transforms using 1-bit systolic arrays

Wafer-Scale Integration of Systolic Arrays

Space-Time Domain Expansion Approach to VLSI and Its Application to Hierarchical Scene Matching

Similar Documents

A novel systolic array structure for DCT

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation

Sequential Hierarchical Scene Matching

Multirate VLSI arrays and their synthesis

A VLSI for real-time linear operations and transforms

Organization of Relational Models for Scene Analysis

Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform

Erratum: Implementation of convolution and Fourier transforms using 1-bit systolic arrays

Wafer-Scale Integration of Systolic Arrays

Space-Time Domain Expansion Approach to VLSI and Its Application to Hierarchical Scene Matching