NDLI: A radix 4 delay commutator for fast Fourier transform processor implementation

Content Provider	IEEE Xplore Digital Library
Author	Swartzlander, E.E. Young, W.K.W. Joseph, S.J.
Copyright Year	1966
Description	The development is described of a semicustom delay commutator circuit to support the implementation of high-speed fast Fourier transform processors based on the radix 4 pipeline FFT algorithm of J.H. McClellan and R.J. Purdy (1978). The delay commutator is a 108000-transistor circuit comprising 12288 shift register stages and approximately 2000 gates of random logic realized with 2.5-micrometer design rule CMOS standard cell technology. It operates at a 10-MHz clock rate, which processes data at a 40-MHz rate. The delay commutator is suitable for implementing processors that compute transforms of 16, 64, 256, 1024, and 4096 (complex) points. It is implemented as a 4-bit-wide data slice to facilitate cocatenation to accommodate common data word sizes and to use a standard 48-pin dual-in-line package.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	702
Ending Page	709
Page Count	8
File Size	1246610
File Format	PDF
ISSN	00189200
Volume Number	19
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Fast Fourier transforms CMOS logic circuits CMOS technology Pipelines Shift registers Logic gates Logic design Clocks Packaging
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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