NDLI: Hardware Task/Processor Scheduling in a Polyprocessor Environment

Content Provider	IEEE Xplore Digital Library
Author	Manner, Reinhard
Copyright Year	1968
Abstract	A special bus structure, the SYNCBUS, is proposed, which supports task scheduling by hardware. It can be used efficiently in multiprocessor-(all processors identical) and polyprocessor-systems (different pools of processors) running real-time multitasking software with a dynamic load distribution. Tasks waiting for execution create prioritized interrupts, which are distributed over all available processors by hardware. An ``optimal'' load distribution, where the tasks of currently highest priority are assigned to the processors of each pool, is automatically set up and updated continually. The SYNCBUS operates independently of the pool sizes; increasing or decreasing the number of processors in case of changing system requirements or faults is possible. Its decentralized structure allows parallel and local handling of task queues and eliminates processor queues. Overhead times are cut down for three reasons: the faster operation of hardware compared to software table searches, avoidance of memory conflicts due to accessing common system tables by multiple processors, and avoidance of scheduling cycles which do not result in an actual reassignment of tasks to processors. A performance analysis using a mathematical model shows that overhead times can be reduced, depending on the system size and the frequency of task switches, by a factor of up to 10².
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	626
Ending Page	636
Page Count	11
File Size	2418459
File Format	PDF
ISSN	00189340
Volume Number	C-33
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Hardware Dispatching Registers Receivers Operating systems Software scheduling Computer architecture hardware support interconnection set MIMD multitasking parallel processing processor management
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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