NDLI: A high-speed four-bit full adder with a resistor coupled Josephson logic

Content Provider	IEEE Xplore Digital Library
Author	Sone, J. Yoshida, T. Abe, H.
Copyright Year	1980
Abstract	A four-bit full adder circuit implemented in resistor coupled Josephson logic (RCJL) has been designed and successfully tested with 173-ps critical path delay. The full adder circuit uses dual rail logic with emphasis on high-speed operation. An experimental four-bit adder circuit was fabricated using lead-alloy Josephson IC technology with a 5-µm minimum feature size and a 7-µm minimum junction diameter. The circuit consists of 80 devices with 264 junctions. The minimum critical path delay for the ripple carry adder was measured to be 173 ps/4 bits. This result demonstrates the RCJL potential for high-speed digital applications.
Sponsorship	IEEE Electron Devices Society
Starting Page	428
Ending Page	429
Page Count	2
File Size	296803
File Format	PDF
ISSN	07413106
Volume Number	4
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1983-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Josephson junctions Adders Coupling circuits Circuit testing Delay Logic testing Rails Logic devices Logic circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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A high-speed four-bit full adder with a resistor coupled Josephson logic