NDLI: Modeling Bus Contention and Memory Interference in a Multiprocessor System

Content Provider	IEEE Xplore Digital Library
Author	Marsan, M.A. Balbo, G. Conte, G. Gregoretti, F.
Copyright Year	1968
Abstract	Stochastic models of contention for shared resources in an experimental multiprocessor prototype are presented and are validated with simulation and measurement results. Three modeling techniques are used (stochastic Petri nets, Markov chains, and queueing networks) that represent the system operations as Markovian stochastic processes. Each technique is best suited to a specific stage of the analysis. An integrated use of these techniques represents a very powerful tool for the performance analysis of multiprocessor systems and provides ways of investigating several extensions of the prototype architecture. Simulation results and measurements performed on the hardware prototype validate the analysis and show that the accuracy of the analytical results is excellent.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	60
Ending Page	72
Page Count	13
File Size	4945081
File Format	PDF
ISSN	00189340
Volume Number	C-32
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1983-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	queueing networks Bus contention Markov chains memory interference message passing multiprocessors performance evaluation Petri nets
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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