NDLI: On Embedding Rectangular Grids in Square Grids

Content Provider	IEEE Xplore Digital Library
Author	Aleliunas, R. Rosenberg, A.L.
Copyright Year	1968
Abstract	The main results in this paper demonstrate that there exist pairs of integers 〈E, D〉 (for "area Expansion" and "edge Dilation," respectively) such that any n-vertex rectangular grid can be embedded into a square grid having at most En vertices, in such a way that images in the square grid of vertices that are adjacent in the rectangular grid are at most distance D apart. Several techniques for "squaring"-up rectangular grids are presented; sample values for the parameter-pair 〈E, D〉 are: 〈E = 1.2, D = 15〉, 〈E = 1.45, D = 9〉, 〈E = 1.8, D = 3〉. Note that these values of E and D hold for all rectangular grids, independent of number of vertices. The quest for these results was motivated by the question of whether or not one could automatically "square up" circuit layouts having aspect ratios very far from unity, without compromising the efficiency of the layout (in terms of area and length of the longest run of wire). The results reported here yield an affirmative answer to this question, at least in an idealized setting. One corollary of the embeddings presented here is that the side-2n½ square "king's-move" grid contains as a subgraph every n-vertex rectangular grid. Another way to think of this result is that this embellished grid can be "programmed" or "personalized," by setting switches, to represent any n-vertex rectangular grid.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	907
Ending Page	913
Page Count	7
File Size	1300821
File Format	PDF
ISSN	00189340
Volume Number	C-31
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1982-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	theory of VLSI layouts Bounding aspect ratios of layouts embedding graphs in grids generic graphs graph embeddings
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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