NDLI: Application of Line-Edge Profile Simulation to Thin-Film Deposition Processes

Content Provider	IEEE Xplore Digital Library
Author	Neureuther, A.R. Ting, C.H. Chen-Yih Liu
Copyright Year	1966
Description	A computer simulation program based on a segment-motion model has been developed to investigate thin-film-deposition processes. This simulation program is used to study the physical phenomena in the thin-film-deposition process as well as the effects of different tooling configurations and operating conditions. The simulated results are compared with experimental results obtained from an electron-gun evaporator with planetary tooling and from a planarizing sputtered quartz system to verify the accuracy of the simulation and to illustrate important phenomena during the deposition process. The simulation program is also used in exploratory studies to find the optimum source angle for step coverage in a typical planetary evaporator. The step coverage is found to change only slightly for wafers at different locations on the planet, but can change significantly depending on the pattern orientation on the wafers if the wafer rotation is not independent of the planet rotation. A study of the sputtered quartz planarization process shows that the growth of different topological features can be accurately predicted from the change in deposition and etching rate as a function of the angle of incidence. In particular, the increased deposition near a conductor edge is attributed to the propagation of a growth front from the sidewall boundary conditions.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	514
Ending Page	520
Page Count	7
File Size	1460234
File Format	PDF
ISSN	00189200
Volume Number	15
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sputtering Computational modeling Circuit simulation Sputter etching Planarization Computer simulation Planets Surface topography Application software Thin film circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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