NDLI: A novel low-power static I/sup 2/L RAM cell using aluminum Schottky clamps

Content Provider	IEEE Xplore Digital Library
Author	de Nie, R.H. Satyadharma, V.A. Poorter, T.
Copyright Year	1966
Description	A novel bipolar RAM cell is introduced, which combines low standby power with high-speed read and write capability. In the standby mode, the operation is entirely static at a power level of less than 1 /spl mu/W/cell. Read and write selection are performed by an increase of cell current, while discrimination is based on the fact that a cell is selected during only a certain period of time. Investigations on exploratory chips containing 4/spl times/1 arrays have demonstrated the feasibility of large arrays, and have shown a minimum read delay of 12 ns, when a sense voltage of 200 mV difference between the bit lines is used. Improvements in cell layout have led to a unit cell area of 2750 /spl mu/m/SUP 2/ using 5 /spl mu/m design rules, which would enable the realization of a 4 kbit RAM on a 15 mm/SUP 2/ chip. Read access and cycle time for this RAM are predicted to be 65 ns and 160 ns, respectively, at a peak power dissipation of 50 mW.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1102
Ending Page	1107
Page Count	6
File Size	961385
File Format	PDF
ISSN	00189200
Volume Number	14
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aluminum Clamps Voltage Flip-flops Delay Schottky barriers Schottky diodes Power dissipation Ion implantation Equivalent circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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