NDLI: Application of simple hardening techniques in system design and verification of survival by EMP and γ tests

Content Provider	IEEE Xplore Digital Library
Author	Brucker, George J.
Copyright Year	1963
Abstract	The design and test verification of this system intended for use on the ground have demonstrated the success of the often quoted EMP and γ hardening techniques such as radio frequency shielded enclosures, single point grounding, shielded cables, surge arrestors, series resistance limiting, and circumvention. All of these simple techniques were applied in the design of the system described in this paper. This paper discusses in some detail the design and the problems associated with four of these techniques, namely series resistance limiting, circumvention, surge arrestors, and hard memory. The system survived exposure to EMP fields of 53 kV/m and dose rates of ≈ 10¹⁰ rads(Si)/s. These results also showed that the failure dose rate for a memory subsystem will be less than the dose rate for the discrete devices if the design does not take circuit interactions with the memory devices into account. Test data predicts that the memory failure level of midrange 10¹⁰ to 10¹¹ rads(Si)/s can be achieved with careful circuit design.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	4949
Ending Page	4952
Page Count	4
File Size	1757811
File Format	PDF
ISSN	00189499
Volume Number	26
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	EMP radiation effects System testing Resistors Surges Current supplies Grounding Cable shielding Circuit testing Radiation hardening CMOS technology
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Current Source for Testing Long Line EMP Surge Arrestors

Radiation-Resistant Power Circuits

1982 NSREC Short Course on Radiation Effects and System Hardening

Radiation Hardened 64-BIT CMOS/SOS RAM

Testing Considerations for Radiation Induced Latchup

Theoretical and Scale Model EMP Response Analysis of Interconnected System Cables

Nuclear-Radiation-Resistant Circuitry Design and Test

CMOS Hardening Techniques

Radiation effects and hardening of MOS technology: devices and circuits

Application of simple hardening techniques in system design and verification of survival by EMP and γ tests

Similar Documents

Current Source for Testing Long Line EMP Surge Arrestors

Radiation-Resistant Power Circuits

1982 NSREC Short Course on Radiation Effects and System Hardening

Radiation Hardened 64-BIT CMOS/SOS RAM

Testing Considerations for Radiation Induced Latchup

Theoretical and Scale Model EMP Response Analysis of Interconnected System Cables

Nuclear-Radiation-Resistant Circuitry Design and Test

CMOS Hardening Techniques

Radiation effects and hardening of MOS technology: devices and circuits

Application of simple hardening techniques in system design and verification of survival by EMP and γ tests