NDLI: A high speed bulk CMOS C/SUP 2/L microprocessor

Content Provider	IEEE Xplore Digital Library
Author	Dingwall, A.G.F. Stricker, R.E. Sinniger, J.O.
Copyright Year	1966
Description	The CDP 1802, single-chip, 8-bit microprocessor is fabricated in C/SUP 2/L, or closed COS/MOS logic, a new structural approach to high-speed bulk silicon COS/MOS logic. In this self-aligned silicon-gate CMOS technology, the gate completely surrounds the drain providing transistor aspect ratios which maximize the transconductance to capacitance ratio and thus allow high on-chip speed. Generally, standard 6-/spl mu/m channel length C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately four times faster than standard CMOS. High density 5-/spl mu/m channel length devices further improve area and speed by factors up to 1.5. The fabrication sequence for C/SUP 2/L devices requires six photomasks (one less than standard CMOS).
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	457
Ending Page	462
Page Count	6
File Size	875155
File Format	PDF
ISSN	00189200
Volume Number	12
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1977-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Logic devices CMOS logic circuits CMOS technology MOSFETs Solid state circuits Logic circuits Counting circuits CMOS process Appropriate technology
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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